; var3.asm
; by renzo diomedi
;
; to verify the values into the registers
;
section .data
;
dquad1 dq 0xfffffffffffffff1
dquad2 dq 0xfffffffffffffff1
dqSum ddq 0
;
;;
section .text
global _start
_start:
;
; ADDITION 128 BIT 
; Each of the variables dquad1, dquad2, and dqSum are 128-bits and thus will exceed 
; the machine 64-bit register size. However, two 64-bit registers can be used for  
; each of the 128-bit values. 
; This requires two move instructions, one for each 64-bit register.
;
; The first move to the rax register accesses the first 64-bits of the 128-bit variable. 
; The second move to the rdx register access the next 64-bits of the 128-bit variable. 
; This is accomplished by using the variable starting address, dquad1 and adding 8 bytes
; thus skipping the first 64-bits (or 8 bytes) and accessing the next 64-bits.
; If the LSQ's are added and then the MSQ's are added including any carry, the 128-bit
; result can be correctly obtained.
;
;
mov rax, qword [dquad1]      ; LSQ least significant quadword
mov rdx, qword [dquad1+8]    ; MSQ most significant quadword, +8 bytes in higher memory
;
add rax, qword [dquad2]
adc rdx, qword [dquad2+8]    ; adc which will add the quadwords and include a carry from 
;                            ; the previous addition operation.
mov qword [dqSum], rax
mov qword [dqSum+8], rdx
; 
;
; Carry bit is part of the rFlag register
; Initially, the LSQ of dquad1 is placed in rax and the MSQ is placed in rdx. Then the
; add instruction will add the 64-bit rax with the LSQ of dquad2 and, in this example,
; provide a carry of 1 with the result in rax. Then the rdx is added with the MSQ of
; dquad2 along with the carry via the adc instruction and the result placed in rdx.
;
;
;
mov rax, 1
mov rbx, 0
int 0x80
